1. Field of the Invention
The present invention relates to a method for fabricating a memory device, and more particularly to a method for fabricating a crown capacitor for a dynamic random access memory (DRAM).
2. Description of the Prior Art
As semiconductor device dimensions get smaller and device density increases, it becomes more and more difficult to provide a capacitor having high capacitance. Recently, a DRAM which has a three-dimensional stack layered capacitor has been developed to increase the capacitance of the capacitor. Referring to FIGS. 1A through 1D, the cross-sectional side views of a conventional method for fabricating a capacitor's bottom electrode are depicted in sequence.
Referring now to FIG. 1A, a cross-sectional view of the first step is schematically shown. In FIG. 1A, an insulated layer 14 is formed on the p-type semiconductor substrate 10 having n-type source 12. The capacitor contact (CC) 16 and conductive plug 18 filled into the capacitor contact 16 are formed in the insulated layer 14 to connect with source 12. Then, a conductive polysilicon layer 20 and BPSG layer 22 are formed on the insulated layer 14. A photo-resist pattern 24 is coated on the BPSG layer 22 by a conventional photolithography process.
Next, as shown in FIGS. 1A and 1B, using the photo-resist pattern 24 as the etching mask, the BPSG layer 22 and polysilicon layer 20 are sequentially etched by anisotropic etching, thereby leaving a block which consists of the BPSG layer 22a and polysilicon layer 20.
Then, as shown in FIG. 1C, a conductive polysilicon layer 26 is formed on the surface of the block described above by low-pressure chemical vapor deposition.
Referring now to FIGS. 1C and 1D, the polysilicon layer 26 formed on the upper surface of the BPSG 22a is removed to leave polysilicon layer 26a. Afterward, BPSG 22a is removed by hydrogen fluoride solution, thereby forming the crown bottom electrode, polysilicon layer 26a and polysilicon layer 20 of the capacitor.
However, the conventional fabrication process for the bottom electrode of the capacitor suffers from problems. For example, the interface of polysilicon layer 20 and polysilicon layer 26a can produce native oxide in the thermal step. As a result, the polysilicon silicon layer 26a is easily stripped during the BPSG 22a removal step.